The speed of image capturing by normal solid-state image sensors is limited by the information transfer capability of a read-out line for reading out image information from the image sensor to the outside of the image sensor. Precisely, the image capturing speed is limited by the information processing capabilities of an output circuit that performs processing preceding the image information read-out and an AD converter that performs processing succeeding the image information read-out, that is, a sampling rate. A standard maximum sampling rate of currently used image sensors is approximately 25 MHz (25,000,000 pixels per second) in 8-bit conversion. For example, when the image information of one hundred thousand or one million pixels arranged on the image capturing area is read out through one read-out line, the upper limit of the image capturing speed is 250 frames per second (25,000,000/1,000,000) or 25 frames per second (25,000,000/1,000,000).
The following two methods have been employed to enhance the speed of image sensors.
One method is to maximize the number of sets of a read-out circuit, a read-out line and an AD converter. The image sensors employing this method are called parallel read-out image sensors. The present inventor has already provided a video camera having a parallel read-out image sensor with 16 read-out lines. The image capturing speed of this video camera is 4,500 frames per second in the case of 256×256 pixels (for example, see Takeharu ETOH, “4500-Per-Frame High-Speed Video Camera”, Journal of the Institute of Image Information and Television Engineers, Vol. 46, No. 5, 1992, pp. 543–549).
The other method is to provide, on the periphery of each pixel, an area where a multiplicity of pieces of image information can be stored, continuously store image information in the image sensor without reading out the image information to the outside of the image sensor during image capturing, and read out the image information with leisure after image capturing is finished. The present inventor calls the image sensors employing this method In-situ Storage Image Sensors (ISISs). Since the ISISs record image information with all the pixels in parallel, ultimate ultrahigh-speed image capturing is possible. For example, in the case of 256×256 pixels where image information is recorded through parallel processing of 65, 536 (256×256), incommensurably high-speed image capturing is possible compared to the parallel read-out from 16 lines.
The present inventor and others have already developed and proposed some ISIS image sensors (for example, see Takeharu ETOH et al., “Improved Design of an ISIS type for a Video Camera of 1,000,000 pps”, Proceedings of High-Speed Imaging and Sequence Analysis, SPIE Vol. 3642, 1999, pp. 127–132).
Many of these ISIS type image sensors use CCDs (charge-coupled devices) as image information storage means.
Normal CCD image sensors are broadly divided into an interline transfer CCD image sensor 10 (referred to as IT-CCD image sensor) shown in FIG. 17 and a frame transfer CCD image sensor 11 (referred to as FT-CCD image sensor) shown in FIG. 18.
In the IT-CCD image sensor, photoelectrical converters 12 (photodiodes are normally used) that convert light to electrical charge and charge transfer paths 13 (storage portions) comprising CCDs are separately disposed on a horizontal plane. Light is intercepted from the charge transfer paths 13 by a non-illustrated intercepting film. Input gates 14 are interposed between the photoelectrical converters 12 and the charge transfer paths 13. The charge generated at each photoelectrical converter 12 in accordance with the intensity of the incident light is transferred to the charge transfer path 13 through the input gate 14. Since the aperture efficiency (the ratio of the area of the non-light intercepted portion of the window with respect to the area of the entire light receiving portion) is decreased due to the provision of the intercepting film, microlenses are attached above the windows to increase the substantial aperture efficiency.
In the FT-CCD image sensor, the charge transfer paths 13 also perform as photoelectrical converters on an image capturing area 15. Non-illustrated transparent electrodes are attached above the charge transfer paths 13, and the charges generated by the light incident through the transparent electrode are transferred by changing the voltages applied to the transparent electrodes. However, since charges are continuously generated according to the incidence of the light during the charge transfer, a light intercepted image information storage area 16 comprising a CCD and corresponding to one frame is provided in a lower part of the image capturing area 15. At the time of image capturing, after exposure is performed for a predetermined time, image information of one frame is transferred from the image capturing area 15 to the image information storage area 16 at an extremely high speed, and the image information is read out to the outside of the image sensor with leisure during the subsequent exposure. The FT-CCD image sensor may be constructed of only a simple CCD. Moreover, since light is incident also on the charge transfer paths 13, the aperture efficiency is high, and therefore, it is unnecessary to attach a microlens.
As described above, the FT-CCD image sensor is simpler in structure than the IT-CCD image sensor because of unnecessity of the input gates and the microlens. For this reason, early CCD image sensors are of the FT-CCD type.
However, the FT-CCD image sensor, which captures incident light through the transparent electrode, is low in the sensitivity to the light in the wavelength range readily absorbed by the transparent electrode. Normally, the transparent electrode is made of polysilicon, and however thin it may be, it largely absorbs blue light with short wavelengths. In addition, since light is incident also during the charge transfer, a so-called smearing, in which portions of an image corresponding to high light-intensity are captured as longitudinally elongated lines, is remarkable. To prevent the smearing, it is necessary to take an artifice such as provision of a mechanical or electrical high-speed shutter for intercepting incident light during the charge transfer on the front surface of the image sensor. Since these problems are significantly improved in the IT-CCD image sensor, many of the recent CCD image sensors are of the IT-CCD type or an improved IT-CCD type.
With respect to the ISIS, the following image sensors are both based on the IT-CCD type: a CCD image sensor shown in FIG. 19 developed by Kosonocky et al. (see F. W. Kosonocky et al., “360×360-Element Very-High Frame-Rate Burst-Image Sensor”, Digest of Technical Papers, ISSC 96, 1996, pp. 182–183); and an image sensor shown in FIGS. 20 and 21 that the present inventor has already proposed (for example, see the above-mentioned document of Takeharu ETOH and three others) Specifically, in these image sensors, each pixel has a large-size photodiode 115 and a CCD type recording portion 135 having a multiplicity of small charge accumulation elements on a side of the photodiode 115. The photodiode 115 and the recording portion 135 are interconnected by an input gate 114.
On the other hand, the FT-CCD type can be used as the basic structure as shown in FIG. 22. In the FT-CCD image sensor shown in FIG. 22, the entire area of the photoreceptive of the FT-CCD image sensor of FIG. 18 is covered with an intercepting film 17, and in the intercepting film 17, windows 18 through which light passes are formed so as to be staggered. Fifteen CCD elements 19b to 19d below each window 18 can be used as image information storage portions because they are covered with the intercepting film. That is, the image information (charge) of a first image generated at the CCD element 19a corresponding to each window 18 is first accumulated in the CCD element 19b immediately below the window 18. Then, the image information of a second image generated at the CCD element 19a corresponding to each window 18 is stored in the CCD element 19b immediately below the window 18 at the same time when the first image information is transferred to the CCD element 19c one row below. By repeating similar processes, image information of fifteen continuous frames is stored in the CCD elements 19b to 19d. After the shutter provided on the front surface of the image sensor is closed, the image information is transferred one after another in a vertical direction as in the normal FFT-CCD image sensors, and the stored image information can be read out one after another with leisure from a read-out circuit through a horizontal CCD provided outside the photoreceptive area. When the FT-CCD image sensor shown in FIG. 22 is employed as the basic structure, the structure of the image sensor is sufficiently simple compared to when the IT-CCD image sensor shown in FIGS. 19 to 21 is employed as the basic structure, so that the manufacturing cost can be reduced and noise can be suppressed.
In FIG. 22, the windows 18 are not arranged so as to form squares. On the other hand, by arranging windows 18 as shown in FIG. 23 and slanting the image capturing area with a gradient of 4:1, the windows 18 form a square arrangement. In this case, the basic axes 36 for designing the CCD and the orthogonal axes 37 of pixel arrangement interconnecting the centers of the windows 18 obliquely intersect with a gradient of 4:1. With the structure of FIG. 23, ISISs of orthogonal pixel arrangement can be easily realized (see Japanese Laid-Open Patent Application No. 2000-268010).
In high-speed image capturing, it is difficult to perform image capturing in exact timing with the occurrence of a phenomenon. For example, although the image sensor of FIG. 22 is capable of continuously image capturing fifteen images, when image capturing is performed at intervals of 1/1,000,000 second with the image sensor, image capturing is finished in 15/1,000,000 second. Therefore, a shift of timing of only 15/1,000,000 second makes it impossible to capture the target phenomenon.
An example of means for solving this problem is serial overwrite image capturing. The serial overwrite imaging is started before the target phenomenon occurs, and finished immediately after the occurrence of the phenomenon is confirmed. The recorded image information is read out retroactively. Comparing a method in which the occurrence of a phenomenon is predicted and image capturing is started immediately before the occurrence and a method in which image capturing is finished after the occurrence of the phenomenon is confirmed, the latter method is by far easier.
To realize this, for example, a drain 38 is provided in the CCD element immediately above each window 18 as shown in FIG. 23. The drains 38 are set so as to function during image capturing and not to function during the information read-out performed after image capturing.
The drains of normal CCD image sensors have roughly two purposes. One is an overflow drain function of making the excessive charge generated by excessive incident light automatically overflow to the outside of the sensor in order to prevent blooming that the excessive charge overflows to surrounding pixels. The other is a simultaneous discharging function of simultaneously discharging the temporarily stored charge to the outside of the image sensor every charge transfer stage. This function is employed, for example, for preventing smearing due to incomplete charge transfer from the photodiode to the CCD transfer path.
In ISISs, drain function for serial overwriting is further added to these. Drains for serial overwriting are a kind of simultaneous discharging drain in structure. However, while electronic shutters and drains for smearing-prevention function every charge transfer step, serial overwriting drains in ISISs are activated immediately before the start of image capturing, held activated during image capturing, and deactivated immediately after the end of image capturing.
Since these drain functions are also very important in ISISs, existing technologies regarding drains will be concretely described. Examples of the drain structure include a vertical drain structure and a horizontal drain structure.
In the vertical drain for the FT-CCD image sensor, electrodes are provided above the CCD elements in the uppermost row of the light intercepted image storage area 16 (39 in FIG. 18). A high voltage is applied to the electrode to thereby transmit charge vertically below the CCD transfer paths, resulting in that the charge is discharged from the rear surface of the chip of the image sensor. The time necessary for merely simultaneously transferring the image information of one frame vertically downward within the image capturing area is sufficiently short compared to the time for storing charges, that is, the time necessary for reading out all of the image information of one frame. The read-out needs long time because image information is read out from the storage portion pixel by pixel after the frame transfer. Therefore, charges can be substantially simultaneously discharged by providing one row of drains on the lower side of the photoreceptive area.
In the vertical drain for the IT-CCD image sensor, a high negative voltage is applied to the chip rear surface, and charge is discharged to the chip rear surface from a portion where a potential barrier is weak, which portion is formed on the lower surface of each photodiode.
On the other hand, in the horizontal drain, the drain is disposed so as to adjoin the charge transfer path or the photodiode, and a potential barrier is interposed therebetween so that no charge flows into the drain in normal phases. When a voltage is applied to the electrode disposed above the potential barrier, the potential barrier decreases, so that charge is discharged from the charge transfer path or the photodiode into the drain on a side thereof. The charge discharged into the drain is further discharged to the outside of the sensor through an electrical wire disposed above the drain. Alternatively, charge may be discharged from the chip rear surface to the outside of the sensor through a portion, immediately below the drain, where the potential barrier is weak.
The drain can be used as an electronic shutter by turning on and off the high voltage applied to the electrode for the drain at an appropriate timing.
By providing a drain 38 in a CCD element 40 immediately above each window 18 as shown in FIG. 23, the information of the image captured at proceeding 16 steps is always continuously discharged from the drain 38 to the outside of the image sensor during image capturing, and the image information corresponding to latest 15 frames is always recorded in a CCD accumulation element.
After image capturing is finished, the shutter provided on the front surface of the image sensor is closed, the application of the drain voltage is stopped so that the drain function is deactivated, and then, the image information stored in the sensor is read out to the outside of the image sensor by a normal CCD operation.
It should be noted that in case of the drain for serial overwriting, a condition where the drain functions is maintained during image capturing whereas a condition where the drain does not function is maintained after image capturing is finished. Concretely, electrodes for activating and deactivating the drain function and power transmission means for transmitting a voltage for the activation and deactivation are newly required. The activation and deactivation are performed not during image capturing but only immediately before and after image capturing.
Normally, disposition of one layer of metal wires or polysilicon wires on the surface of the image sensor is necessary for operating the voltages transmitted to the electrode. By applying the voltages to the drain electrodes through these wires, charges are discharged from the rear surface of the image sensor through the drain. The addition of one layer of wires is an enormous load because the smaller the number of conductive films for forming electrodes on the image sensor, the easier the design and fabrication are.
In the case of the vertical drain, since the voltage is normally applied from the chip rear surface, it is unnecessary to further provide a wiring on the chip surface. However, since the drains for these purposes including the drain for the electronic shutter serving the three purposes of simultaneous discharging, drain for overflow, and drain for serial overwriting have different operations and positions of placement from one another, it is difficult to realize all the three functions only with the activation and deactivation of the voltage applied to the chip rear surface and the voltage level control. If the vertical drain control voltages can be transmitted not only from the rear surface of the chip but also from the upper surface thereof, it will become by far easy to control these functions in combination.